d e v i c e o v e r v i e w > applications ? digital video recorders (dvr) ? video mixers and switchers ? surveillance / cctv cameras ? industrial and professional cameras ? digital image transfer / capture devices ? distribution amplifiers ? repeaters m080 4 5 M08045 serial digital video reclocker for 2.97 gb/s, 1.485 gb/s , and 270 mb/s data rates 3g/hd/sd serial digital video reclocker figure 1 C m0804 5 pin - out diagram product brief the M08045 is a serial digital video reclocker with integrated trace equalization , automatic rate detect (ard) circuitry , and a 4:1 mux at the input . it operates at data at 2.97 gb/s, 1.485 gb/s, and 2 70 mb/s . the device has an input jitter tolerance (ijt) of greater than 0.6 unit intervals (ui) and can provide retimed serial outputs with very low output jitter. the reclocker requires a single, external, 27mhz crystal, which is used as the reference clo ck for all four channels. it includes per lane analog input equalization for up to 40" of fr4 trace and two connectors in addition to output de - emphasis. this device features integrated supply regulators, allowing it to be powered from 1.2v, 1.8v, 2.5 v, o r 3.3 v supply voltages. when operating at 1.2 v, it consumes only 230 mw . furthermore, the power rails for the core, input, and output circuitry are electrically independent thus may be connected to different voltage rails on the board. this fe ature enables the M08045 to be dc coupled to any upstream or downstream device regardless of its input/output voltage level. the 4:1 mux at the input allows any of the 4 inputs to be routed to the integrated reclocker and its output. the device , and the i nput mux, may be configured by setting the internal registers th r ough standard two - wire and four - wire interfaces. optionally, the reclocker may be configured at power - up through an external eeprom device . limited configuration through hardware pin settings is also available.
features benefits 0.6 ui input jitter tolerance enable robust, error free designs optimized data rate s at 270 mb/ s, 1.485 gb / s , and 2.97 gb/s single chip solution for multiple data rates integrated 50 ? input termination save s board area and enable high density designs 4:1 input multiplexer enables high density designs, flexibility , low cost input equalization up to 40 of fr4 trace and 2 connectors , and output de - emphasis ease of high speed design and layout integrated reg ulators extending operation from 1.2v to 3.3v reduces number of power rails required on board electrically isolated input, output, and core supply rails allows dc interface which saves board area and cost automatic and manual modes for rate indication an d selection ease of use and flexibility loss of lock (lol), loss of signal (los), and data rate indication ease of status update and diagnostics low power dissipation (230mw at 1.2v) low power and thermal management costs small form factor and foot prin t (6x6 mm2, 40 - pin qfn package) industry standard package industrial operating temperature range: C 40c to +85 c provides higher tolerance and additional design margin t e c h n i c a l d et a i l s ? 201 1 mindspeed technologies, inc. all ri ghts reserved. mindspeed and the mindspeed logo are trademarks of mindspeed technologies. all other trademarks are the property of their respective owners. although mindspeed technologies strives for accuracy in all its publications, this material may cont ain errors or omissions and is subject to change without notice. this material is provided as is and without any express or implied warranties, including merchantability, fitness for a particular purpose and non - infringement. mindspeed technologies shall n ot be liable for any special, indirect, incidental or consequential damages as a result of its use. www.mindspeed.com/salesoffices general information: (949) 579 - 3000 headquarters C newport beach 4000 macarthur blvd., east tower newport beach, ca 92660 - 3007 for more product information, please visit www.mindspeed.com package (rohs compliant) ? 6 x 6 mm2, 40 - pin qfn figure 2 C m0804 5 functional block diagram
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